1. Field of the Invention
The present invention is directed to a polycrystalline semiconductor thin film layer and the method of production thereof, to a semiconductor device and the method of production thereof, and to an electronic apparatus, more specifically to an effective technology suitable for application in manufacturing transistors on the surface of polycrystalline semiconductor thin film layer (thin film transistors, TFT), polycrystalline layer for producing the thin film transistors, and electronic devices such as liquid crystal display devices or information processing devices incorporating the thin film transistors.
2. Description of the Related Art including information disclosed under 37 CFR 1.97 and 37 CFR 1.98:
Thin film transistors (TFT) used heretofore in the conventional image display devices and the like have been formed on a substrate material such as amorphous silicon or microcrystalline silicon made by means of plasma CVD on an insulating substrate of glass or quartz, with the polycrystalline silicon as element material made by means of melt and recrystallization method such as excimer laser annealing.
TFT made of polycrystalline silicon as material has field effect mobility of 100 to 200 cm2/Vsec due to decreased mobility caused by the carrier scattering in the grain boundary, in comparison with the field effect mobility ideal in the single-crystalline silicon (Japanese Unexamined Patent Publication No. H9-27452). The mobility is approximately 500 cm2/Vsec in single-crystalline silicon MOS-FET (S. M. Sze, Physics of Semiconductor devices, Second Edition, Wiley, P449)
The position and the number of crystal grains formed on the channel of a transistor is not controllable and hence the device performance is not uniform compared to the single-crystalline silicon MOS-FET (Japanese Unexamined Patent Publication No. H10-291897).
Numerous techniques have been devised and proposed for enlarging the size of grains and for controlling the position of them. These techniques include, among others, a method for solid-state crystallization of amorphous silicon using the islet-patterned nuclei formed on the insulating substrate (Japanese Unexamined Patent Publication No. H8-316485), a method for forming a deposited amorphous layer on a polycrystalline silicon and making use of polycrystalline silicon exposed on the surface as the nuclei for next solid phase crystallization (Japanese Unexamined Patent Publication No. H8-31749), a method for selectively producing amorphous layers from partially crystallized silicon thin film by using ion-implantation and making use of the residual crystallization as nuclei for recrystallization (Japanese Unexamined Patent Publication No. H10-55960), a method for accelerating the rate of crystallization by diffusion of metal elements (Japanese Unexamined Patent Publication No. H9-27452), and a method for gradually altering the irradiating energy and irradiation period of time of pulse laser annealing (Japanese Unexamined Patent Publication No. H10-97993).